Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit

The downscaling of silicon field-effect transistors is approaching fundamental limits, with the international roadmap for devices and systems (IRDS) projecting a 12 nm channel length plateau by 2037. Two-dimensional (2D) semiconductors have emerged as promising candidates for extended transistor scaling. However, no experimental demonstration has thus far surpassed the fundamental switching limits of advanced silicon. Here, we report monolayer MoS₂ transistors with physical channel lengths below 5 nm, achieving a subthreshold swing of 88 mV/dec and an on/off ratio above 106. These results surpass both the theoretical subthreshold limit of silicon and state-of-the-art emerging semiconductors-based transistors at comparable dimensions. To ensure high throughput, we develop a photolithography based, complementary metal oxide semiconductor (CMOS) compatible process and demonstrate 4-inch wafer-scale integration. We implement a design–technology co-optimization approach featuring an air-gap isolation and gate-contact overlap design to effectively suppress short channel effects. This work demonstrates subthreshold transport in a 2D semiconductor transistor beyond the silicon limit, showing a viable pathway for extending transistor scaling and energy-efficient computing. 2D semiconductors have emerged as promising candidates to extend Moore’s law beyond silicon limits. Here, the authors report the fabrication of wafer-scale monolayer MoS2 transistor arrays with sub-5 nm channel length and optimized design of the dielectric environment to suppress short channel effects.