Beyond SiO2: A Review of Advanced High Dielectric Constant Passivation Layers for 4H-SiC Metal-Oxide-Semiconductor Devices

Abstract The relentless pursuit of higher efficiency, power density, and temperature capability in power electronics has positioned 4H-silicon carbide (4H-SiC) as a cornerstone semiconductor for next-generation devices. While the existence of a native SiO2 layer had facilitated the development of 4H-SiC metal-oxide-semiconductor (MOS) technology, this insulator was ultimately identified as a constraint on its ultimate performance. The significant dielectric constant (k) mismatch between SiO2 (k = 3.9) and 4H-SiC (k = 9.7) results in a much higher electric field within the oxide, thereby limiting the full exploitation of the high critical field of 4H-SiC. Furthermore, the inherently high interface trap density (Dit) at the SiO2/SiC interface severely degraded channel mobility and device reliability. This review comprehensively charted the trajectory of advanced high-k passivation layers designed to surmount these fundamental limitations. This review presented a critical assessment of a wide spectrum of alternative dielectrics, including Al2O3, AlN, HfO2, ZrO2, and rare-earth oxides, based on stringent criteria such as band alignment, thermodynamic stability, and interface quality. The pivotal role of post-deposition annealing in passivating interface states and modulating electrical properties was thoroughly examined. By synthesizing the current state of the art and highlighting emerging materials and interface engineering strategies, this review provided a roadmap for the development of robust high-k dielectrics on 4H-SiC, which is crucial for unlocking the full potential of ultra-high-voltage, high-temperature, and radiation-hardened power devices.