An Evidence-Based Framework for Hardware Security Evaluation Using Side-Channel Analysis: Leakage Detection, Key-Recovery Validation, and Robustness Assessment

Side-channel analysis (SCA) remains a significant threat to embedded cryptographic implementations, yet hardware security evaluation often lacks a systematic workflow that links leakage detection, exploitability validation, trace-efficiency estimation, and robustness assessment. Rather than proposing a new leakage distinguisher, this work presents an evidence-based framework that integrates established SCA techniques into a reproducible hardware security evaluation methodology for embedded AES implementations. The proposed framework follows a structured screen–validate–quantify–stress-test pipeline. Power traces are acquired from an AES-128 implementation on a CW312/SAM4S target using a shunt-based measurement path and firmware-triggered ChipWhisperer–Husky acquisition. Fixed-versus-random test vector leakage assessment (TVLA) using 5000 fixed and 5000 random traces reveals strong first-order leakage, with a dominant peak of |t| = 210.61 at sample index 1916, defining a leakage window of [1666:2167]. Exploitability is validated through timing-aware per-byte correlation power analysis (CPA) under a Hamming-weight leakage model, successfully recovering the full AES-128 key and revealing staggered byte-wise leakage timing for point-of-interest selection. Operational feasibility is quantified through 100 independent subsampling trials over trace budgets M ∈ {25, 50, 75, 100, 150, 200, 300, 400, 700, 1000}, achieving 97% full-key recovery with 25 attack traces and 100% recovery from 50 attack traces onward when using pre-established byte-specific POIs. Independent split-data point-of-interest validation further confirms the stability and reproducibility of the selected leakage locations. Finally, controlled synthetic timing-misalignment experiments evaluate robustness by measuring recovery degradation, weakest-byte confidence behaviour, and the effect of local peak-search compensation under non-ideal analysis conditions. Collectively, this case study demonstrates a reproducible SCA evaluation workflow on the investigated CW312/SAM4S AES-128 implementation, integrating leakage screening, exploitability validation, trace-efficiency analysis, independent POI validation, and controlled robustness testing. The present results establish the workflow on this experimental platform, but evaluation across additional devices, firmware implementations, keys, acquisition sessions, and protected implementations is required before broader generalisation can be claimed.