Design and FPGA implementation of an area and throughput-efficient LDPC encoder architecture using Python-based VeCoGen

Modern high‑speed cellular communication systems, the major requirement is reliable error correction in wireless networks for the next‑generation network, such as 5G and satellite communication with high coding gain and high throughput. To achieve these requirements, the low-density parity-check (LDPC) encoders/decoders have become a widely used technology to provide a reliable solution. This paper presents the design and FPGA implementation of VeCoGen, a novel Python-based automated Verilog code generation framework for area- and throughput-efficient LDPC encoders targeting 5G New Radio (NR) base graphs BG1 and BG2. The principal contributions of this work are (i) compile-time shift resolution, (ii) sparsity-aware XOR-tree construction and (iii) an integrated LFSR-based verification mechanism. The proposed architecture is synthesised and functionally verified in Xilinx Vivado 2022.1, targeting the Artix-7 (XC7A100T-2FBG676C) FPGA at a constrained clock frequency of 200 MHz. Synthesised report shows that the proposed LDPC is improved 36.1% by LUT utilisation, 17.5% reduction in CLB utilisation, 22% improvement in throughput and reduction of 22.4% in power consumption as compared to the baseline design. This proposed system supports the configurable lifting factor Z = 3, 6, 12, 24 and enables fast operation. Also, this optimised LDPC encoders will be used to configure the 5G New Radio and beyond.