Adaptive Scale-Aware Post-Processing Refinement for FPGA Placement

FPGA placement maps circuit elements to legal heterogeneous sites while minimizingtotal half-perimeter wirelength (HPWL). Analytical placers such as DREAMPlaceFPGAproduce high-quality global placement and legalization results, but their detailedplacement stage performs only greedy local search, leaving measurable quality onthe table -- most notably for small circuits. We present an adaptive scale-aware post-processing refinement framework that takesDREAMPlaceFPGA's legalized output as the initial solution and selects itsoptimization strategy from circuit scale: for small circuits (fewer than 50Kmovable instances) it applies multi-round simulated annealing with window-baseddetailed placement; for large circuits it applies a GPU-batched detailed placement(GPUBatchDP) that evaluates tens of thousands of candidate moves per iterationusing PyTorch scatter_reduce. On the four ISPD 2016 benchmarks, measured with the same weighted-HPWL metric(w_x = 0.7, w_y = 1.2) applied to both sides, the framework reduces HPWL by25.9% +/- 0.3% on FPGA-example1 (mean +/- std over five random seeds) and by 5.8%,1.4% and 3.9% on the remaining three. On FPGA-example1, 92% of the total HPWL gainis obtained within the first 12% of the runtime. All refined placements remainfully legal (zero overlap and zero site-type violations), verified exhaustively. This record is also available as a preprint. Code: see related GitHub repository.