Chiral Topological Edge Routing for Thermal Mitigation and Bisection Decongestion in 2D Mesh Networks-on-Chip

CTER (Chiral Topological Edge Routing) introduces a geometric routing paradigm for two-dimensional mesh Networks-on-Chip, designed to address central thermal hotspots and bisection congestion in multi-core and many-core architectures. Unlike conventional Dimension-Order Routing, where long-range traffic frequently crosses the central region of the silicon die, CTER treats the physical boundary as an active communication resource. Local traffic continues to follow standard minimal Manhattan paths, while longer-range flows are selectively redirected through a dedicated bidirectional perimeter express route, reducing traffic concentration in the central cores. The architecture uses a deterministic, static core-bypass mechanism combined with a layered Virtual Channel allocation protocol. Formal analysis establishes deadlock- and livelock-freedom by maintaining an acyclic channel dependency graph under Dally-Seitz theory, without relying on runtime routing tables or complex dynamic arbitration. The repository includes simulations across a broad range of network sizes and traffic conditions, including uniform all-pairs and adversarial workloads designed to stress network bisection. Results demonstrate a significant improvement in central core decongestion, with reductions in both mean traffic load and peak central concentration that become increasingly pronounced as network size grows. The repository provides the complete simulation suite, architectural documentation, formal proofs, and licensing information to support independent reproduction and further research.