Logic‐Native Ferroelectric Transistor Arrays for Neuromorphic Edge Vision

ABSTRACT Neuromorphic edge vision seeks to reduce data movement by extracting compact and decision‐relevant features close to the sensor. Most in‐sensor and in‐memory hardware, however, has been designed around synaptic weighting and multiply‐accumulate operations, whereas early visual perception also relies on local comparison, thresholding, and Boolean decisions. Here, we present a topology‐reconfigurable ferroelectric field‐effect transistor array for logic‐native front‐end visual computing. Remanent ferroelectric polarization programs reconfigurable in‐plane junctions in a van der Waals heterostructure, enabling dual‐mode operation as programmable transistors or non‐volatile logic‐memory elements. This device‐level programmability supports functionally complete Boolean operations in a compact two‐cell unit, while transistor‐mode cells act as reconfigurable interconnects for cascaded and parallel logic execution. Using this architecture, we implement hardware logic convolution that maps local spatial correlations into Boolean operations for in situ feature extraction. The logic‐processed outputs are intrinsically binarized, reducing data bit‐width and computational complexity while preserving discriminative visual information. The system achieves ultralow energy consumption (≈2.2 fJ per operation), improves CIFAR‐10 classification accuracy from 93% to 98% under the tested pipeline, and reduces computational cost by more than 50 times. This work establishes a complementary neuromorphic hardware primitive for edge vision, extending device‐level intelligence beyond synaptic MAC toward reconfigurable logic‐based visual preprocessing.