Strategies and Challenges in Memristor‐Selector Integration for High‐Density Memory and Compute‐in‐Memory Systems

ABSTRACT Memristor crossbar arrays offer ultrahigh integration density and exceptional area efficiency, establishing a promising platform for data storage and compute‐in‐memory (CIM) architectures, including neuromorphic and analogue vector–matrix multiplication (VMM) accelerators. Their compact 4F 2 footprint and compatibility with 3D stacking enable dense, low‐latency compute‐in‐memory architectures can alleviate the von Neumann bottleneck. By emulating large‐scale synaptic networks, these arrays support brain‐inspired information processing with reduced energy consumption. However, large‐scale implementation remains constrained by parasitic sneak‐path currents, which induce unintended conduction through neighboring cells, degrade read–write fidelity, and increase power dissipation. This review presents a systematic analysis of resistive‐switching mechanisms and current–voltage characteristics, clarifying the non‐linear relationship between switching parameters and synaptic functionality. We evaluate key performance metrics across state‐of‐the‐art memristors, highlighting progress toward femtojoule‐level switching energies and biologically comparable efficiency. Comparative assessments of transistor‐ and memristor‐based synapses further elucidate energy–performance trade‐offs in CIM hardware. We then examine selector‐integration strategies in one‐transistor–one‐memristor and one‐diode–one‐memristor architectures, with emphasis on rectification strength, threshold nonlinearity, bidirectional plasticity, and back‐end‐of‐line compatibility. As a result, we identify intrinsically bidirectional, scalable selector–memristor co‐design as a critical pathway toward robust, low‐power memristor CIM and neuromorphic crossbar systems.