Low-Power Dynamic Logic Multiband Flexible Integer-N Divider for WLAN Frequency Synthesizers Using a 32/33/47/48 Multimodulus Prescaler

Multiband wireless transceivers require frequency synthesizers capable of supporting more than one operating band without a proportional increase in power, area, and clock-distribution complexity. This paper presents a low-power single-phase-clock flexible integer-N divider based on pulse-swallow architecture. The design integrates a wideband 2/3 prescaler, a 32/33/47/48 multimodulus prescaler, a 7-bit programmable P-counter, and a 6-bit swallow S-counter. The central low-power mechanism suppresses unnecessary switching and short-circuit current in the first flip-flop path during divide-by-2 operation, while the multimodulus stage extends the divider to both the 2.4-GHz and 5–5.825-GHz bands without adding another prescaler flip-flop. The source design reports more than 50% prescaler power saving in divide-by-2 mode and a 6.5-GHz maximum operating frequency for the wideband prescaler. The architecture was modeled in Verilog HDL, functionally evaluated in ModelSim, and synthesized using Xilinx ISE. The supplied FPGA synthesis report indicates a 4.187-ns minimum clock period (238.829 MHz), 1026 slice registers (5%), and 3562 slice LUTs (18%) on an XC5VLX30-3-FF324 target. The results demonstrate the structural feasibility of a programmable single-clock multiband divider, while also revealing that the current top-level FPGA test configuration must be reduced or serialized to satisfy physical I/O limits.