Design and Implementation of a Power-Efficient HML-BIST Architecture for BCD Multiplier Testing

Built-in self-test (BIST) reduces dependence on external test equipment by generating test patterns and evaluating responses on-chip. However, conventional pseudo-random BIST can produce excessive switching activity during test, increasing test power and potentially creating misleading failures in deeply integrated VLSI systems. This paper presents an HML-BIST architecture for a BCD multiplier test environment that combines linear-feedback shift-register (LFSR) based pattern generation, explicit activity-factor control, RAM-based storage, and a space comparator for response verification and fault indication. Separate LFSR paths are used to exercise write data, write address, and read address operations, while the activity-control mechanism regulates pattern transitions. Stuck-at-0 and stuck-at-1 conditions are modeled in HDL and detected by comparing the response of the circuit under test with stored reference data. The design is implemented and evaluated in Xilinx ISE on a Virtex-6 target. The synthesis report shows 512 slice registers, 12,142 slice LUTs, 348 fully used LUT-FF pairs, 24 bonded I/Os, two clock buffers, and one DSP48E1. The reported critical path delay is 0.511 ns, consisting of 0.232 ns logic delay and 0.279 ns routing delay, while the power report gives a total power of 1.065 W. Compared with the baseline values included in the source design report, the proposed HML-BIST uses fewer slice registers and LUT-FF pairs and substantially lower reported power. The results demonstrate that activity-aware pseudorandom testing can provide a practical low-overhead self-test mechanism for multiplier-oriented FPGA designs.