ML-assisted Design Technology Co-Optimization Framework for Advanced Process Nodes: Analysis and Exploration of DTCO Parameters using PPA of Digital Blocks

Design and technology co-optimization (DTCO) is the process of optimizing technology and design concurrently to enhance the performance, power, and area (PPA) of semiconductors, in which an essential ingredient is to evaluate technologies, design rules, and cell architectures using block-level PPA analysis. In this paper, we propose a novel DTCO framework assisted by machine learning (ML) for advanced process nodes. The key features of our framework are: (1) precise analysis of DTCO parameter changes in real time as well as identification of optimal DTCO parameter configurations within an acceptable runtime; (2) a full exploration of PPA metrics through standard cell (SC) library generation and PPA evaluation, for which we develop a new algorithm that accelerates the necessary physical design process; (3) supporting both Complementary-FET (CFET)-based SCs and multi-row-height SCs. Through experiments with benchmark circuits, we show that our DTCO framework preserves trends in PPA changes and precisely identifies optimal DTCO parameter sets while substantially improving efficiency. In addition, it is shown that our SC layout generator supporting CFET-based SCs and multi-row-height SCs provides a timely DTCO process relevant to ongoing technology advancements.