SCALABLE FPGA-BASED DEEP LEARNING ACCELERATOR USING TILED MATRIX MULTIPLICATION AND PIPELINED PROCESSING

Deep neural networks provide strong performance in recognition, prediction, and representation-learning tasks, but their computational intensity and memory-access requirements make efficient deployment difficult on conventional processors. This paper presents a publication-oriented formulation of a scalable Deep Learning Accelerator Unit (DLAU) implemented on a field-programmable gate array (FPGA). The architecture targets the dominant kernels of deep learning workloads by combining tiled data processing, explicit on-chip buffering, streaming communication, and a three-stage fully pipelined datapath. The processing chain consists of a Tiled Matrix Multiplication Unit (TMMU), a Part Sum Accumulation Unit (PSAU), and an Activation Function Acceleration Unit (AFAU). Tiling decouples the supported neural-network size from the fixed amount of FPGA arithmetic resources, while FIFO buffering and pipelined execution allow the three units to operate concurrently. Profiling data in the source design shows that matrix multiplication accounts for 98.6%, 98.2%, and 99.1% of the runtime of feedforward, restricted Boltzmann machine, and back-propagation operations, respectively, motivating the emphasis on a reusable matrix-processing engine. The available FPGA prototype results report a speedup of up to 36.1× over an Intel Core2 processor with a power consumption of approximately 234 mW. The resulting architecture demonstrates how data locality, resource reuse, and coarse-grained pipelining can be combined to build a flexible accelerator for large-scale deep-learning workloads under the area, memory, and energy constraints of reconfigurable hardware.