CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding

Computations related to intra prediction and transform in High Efficiency Video Coding are highly computational demanding, especially when multiple intra prediction modes have to be computed for block-based image encoding. In this paper, we propose a parallel CUDA implementation of HEVC intra frame prediction and integer transform operations on an embedded GPU platform. The presented implementation parallelizes HEVC intra prediction modes (35 in total, divided into planar, DC, and angular modes) and implements an efficient transform computation utilizing shared memory allocation. The proposed implementation was tested on NVIDIA Jetson Xavier NX platform using standardized test images and various quantization parameter settings. The results demonstrate that our solution accelerates the computations by up to 105.17× in terms of kernel computations compared to the sequential CPU implementation. Taking into account CPU–GPU memory transfer and synchronization overheads, the acceleration factor for the end-to-end process is 1.62×. In terms of the reconstructed image quality, there is a small decrease in the average PSNR value equal to about 0.65 dB. It is mainly caused by implementation-related differences in parallel computation, rounding, and quantization procedures. These results show that intra-frame prediction and transform stages in HEVC video codec can be efficiently parallelized using CUDA; however, there are still memory transfer and synchronization overheads limiting end-to-end performance. Our implementation can serve as a building block of a fast HEVC encoder but not as a full-fledged video encoder itself. Source code and dataset for this research are freely available on Zenodo with the DOI: https://doi.org/10.5281/zenodo.17286247.