Limits of Static Defect-Aware Relocation in Open ASIC Physical Design: A Pre-Specified Paired Recovery Experiment
Defect-aware physical-design recovery assumes that identifying an unusable resource can enable functionality to be recovered by relocation. This work tests a narrower question: can a frozen static-vacancy relocation method outperform a qualified native re-legalization control when both are applied to the same failed-footprint cases? HAL FAB SOFTWARE v0.93.5 was evaluated in a pre-specified paired experiment on an open SKY130 HD / GCD physical-design flow. The confirmatory set contained 60 fresh cases; the protocol, expectations, execution ordering, endpoint contract, and artifact identities were frozen before confirmatory execution and preserved with SHA-256-bound records. B2_OPENROAD_NATIVE recovered 60/60 cases, whereas HAL recovered 56/60. The paired table contained 56 both-pass cases, four B2-only successes, zero HAL-only successes, and zero joint failures. The frozen primary two-sided exact McNemar test gave p = 0.125; a post-protocol mid-p sensitivity analysis gave p = 0.0625. The primary test therefore did not reach alpha = 0.05, and the pre-specified HAL recovery-advantage hypothesis was not supported. All four HAL failures were zero-candidate cases. Post-hoc analysis showed that they were the four largest required contiguous site spans in the confirmatory set: 24, 24, 21, and 19 sites, compared with a largest candidate-bearing span of 16 sites. This pattern motivates, but does not prove, a mechanism in which static vacancy enumeration loses coverage when long contiguous free-site spans are absent, while a native legalizer can create feasible space by bounded movement of neighboring cells. The study contributes a reproducible negative-result evaluation and a bounded hypothesis about post-fault actuation freedom rather than a claim of generalized HAL superiority.
Authors
- Seojun Yoon
Publication Details
- Journal
- Zenodo (CERN European Organization for Nuclear Research)
- Published
- 2026-09-13
- DOI
- https://doi.org/10.5281/zenodo.22733762
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- preprint