Statistical variability and performance trade-offs induced by 3D line edge roughness in 12-nm 3-stacked nanosheet FETs

Purpose This paper aims to introduce a statistical investigation for the three-dimensional line edge roughness (LER) resulting variation of 12 nm three-stacked nanosheet field-effect transistors. Design/methodology/approach An experimentally calibrated simulation framework is used to analyze 30 different LER profiles to gain insight into the electrostatic degradation on transport characteristics of devices and circuit level performance. Findings It is shown that the geometrical changes caused by LER create current conduction paths locally which led to threshold voltage (Vt) roll-off, drain-induced barrier lowering (DIBL), degradation of subthreshold swing (SS) and reduction of transconductance. There is a significant correlation between DIBL, threshold voltage and SS and it indicates that electrostatic degradation plays the main role in increasing the variability in the stacked nanosheet devices. A compromise of the two is certainly observed as well, and leakage current is far more sensitive to LER than drive current. The ION coefficient of variation (CV) is only 0.60% versus the CV of IOFF, which exhibits a massive variation of 27.5%, indicating that leakage current is the most critical variability issue. Originality/value It additionally presents one yield based interpretation of the parameter changes due to LER, and shows that electrostatic integrity is one of the critical issues to consider when designing nanosheet transistors with variability in mind. These results overall highlight the need for managing LER in future nanosheet based technologies to provide good performance, reliability and manufacturability.