Design and analysis of 10T and 16T hybrid full adder for AI/ML applications

The present research demonstrates the modelling and analysis of 10T and 16T hybrid full adders designed employing FinFET technology for low‑power AI/ML operations. The demonstrated full adder designs have been implemented utilising Gate Diffusion Input (GDI) technique. This project investigated the 10T and 16T full adders for the power–delay product (PDP), delay and power dissipated with pre‑layout as well as post‑layout simulations. The proposed designs are implemented with 18 nm FinFET technology node and 45 nm CMOS technology node utilising the Cadence Virtuoso Tool. The novelty of this work lies in combining GDI logic with FinFET devices and proposing an ultra-compact 10T architecture that achieves a superior PDP compared to existing adders. Additionally, the enhanced 16T structure introduces a rail-to-rail correction mechanism and includes temperature-aware analysis that is rarely explored in prior studies. The designed 10T and 16T full adders have shown improved performance in terms of power, delay and PDP in contrast to previously available full adders. The proposed full adders have shown a tremendous performance for low‑power and AI/ML applications.