Design and optimization of strip-level fan-out packages with fine-pitch redistribution layers

As electronic systems demand ever higher levels of integration, fan-out (FO) packaging has become essential for enabling high input/output (I/O) density, miniaturization, and heterogeneous integration. Although wafer- and panel-level FO architectures offer enhanced scalability and cost-effectiveness for large-area manufacturing, the literature contains little information on balancing fine-line redistribution layer (RDL) designs with the need for mechanical stability and long-term reliability under thermomechanical stress. To address this problem, this study presents a strip-level fan-out (FO-Strip) package featuring a die-last architecture that facilitates superior RDL definition with a line/space resolution of 5 μm/5 μm. With a fan-out region of 36.5 mm × 29.5 mm and a substrate measuring 50 mm × 50 mm, the proposed package design combines the scalability advantages of panel-level production with enhanced manufacturability and cost effectiveness. To enable systematic multi-parameter design optimization, a three-dimensional finite element (FE) model is developed to simulate the thermomechanical response of the package during assembly and JEDEC-standard thermal cycling at −40°C to 125°C. The simulation results for the out-of-plane warpage are shown to be consistent with the experimental data obtained from shadow Moiré measurements. A response surface methodology (RSM) technique with a Box–Wilson central composite design is applied to examine the effects of the die thickness, heat sink thickness, and thermomechanical properties of the encapsulant (EMC), substrate core, and underfill material on the warpage and plastic work accumulation during thermal loading. The results show that increasing the die and heat sink thicknesses and optimizing material properties (reducing the CTE mismatch between the FO package and the substrate) reduce package warpage by 41.4% and solder joint plastic work density by 53.4%. Overall, the proposed design and optimization framework provides useful practical guidelines for improving the thermomechanical reliability of large-area fan-out packages and establishes a predictive platform for next-generation heterogeneous integration applications.

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Publication Details

Journal
Materials Science in Semiconductor Processing
Published
2026-09-11
DOI
https://doi.org/10.1016/j.mssp.2026.111160
Primary Topic
Electronic Packaging and Soldering Technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

Design and optimization of strip-level fan-out packages with fine-pitch redistribution layers

Wei-Han Chen, I-Hung Lin, Meng-Kai Shih, Chung‐Chih Lin et al.
Materials Science in Semiconductor Processing
Electronic Packaging and Soldering Technologies
article

Design and optimization of strip-level fan-out packages with fine-pitch redistribution layers

Wei-Han Chen, I-Hung Lin, Meng-Kai Shih, Chung‐Chih Lin, Bo-Rui Ding, Tom Ni
article en

Abstract

As electronic systems demand ever higher levels of integration, fan-out (FO) packaging has become essential for enabling high input/output (I/O) density, miniaturization, and heterogeneous integration. Although wafer- and panel-level FO architectures offer enhanced scalability and cost-effectiveness for large-area manufacturing, the literature contains little information on balancing fine-line redistribution layer (RDL) designs with the need for mechanical stability and long-term reliability under thermomechanical stress. To address this problem, this study presents a strip-level fan-out (FO-Strip) package featuring a die-last architecture that facilitates superior RDL definition with a line/space resolution of 5 μm/5 μm. With a fan-out region of 36.5 mm × 29.5 mm and a substrate measuring 50 mm × 50 mm, the proposed package design combines the scalability advantages of panel-level production with enhanced manufacturability and cost effectiveness. To enable systematic multi-parameter design optimization, a three-dimensional finite element (FE) model is developed to simulate the thermomechanical response of the package during assembly and JEDEC-standard thermal cycling at −40°C to 125°C. The simulation results for the out-of-plane warpage are shown to be consistent with the experimental data obtained from shadow Moiré measurements. A response surface methodology (RSM) technique with a Box–Wilson central composite design is applied to examine the effects of the die thickness, heat sink thickness, and thermomechanical properties of the encapsulant (EMC), substrate core, and underfill material on the warpage and plastic work accumulation during thermal loading. The results show that increasing the die and heat sink thicknesses and optimizing material properties (reducing the CTE mismatch between the FO package and the substrate) reduce package warpage by 41.4% and solder joint plastic work density by 53.4%. Overall, the proposed design and optimization framework provides useful practical guidelines for improving the thermomechanical reliability of large-area fan-out packages and establishes a predictive platform for next-generation heterogeneous integration applications.

Materials Science in Semiconductor ProcessingVol. 217
De Lin Institute of Technology (TW), National Formosa University (TW), National Cheng Kung University (TW)
National Science and Technology Council
Industry, innovation and infrastructure
Openalex Percentile: Top 20%
Electronic Packaging and Soldering Technologies
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