Leakage Assessment and Correlation Power Analysis of the MAYO Secret Linear Map on a Cortex-M4: A Reproducible Case Study and a Validated First-Order Countermeasure

This work presents a complete power side-channel evaluation of the MAYO secret linear map on a constrained embedded target, together with a first-order countermeasure evaluated on the same hardware. While MAYO ranks among the most embedded-friendly candidates in the National Institute of Standards and Technology (NIST) additional-signatures call, few countermeasures for it are quantified against an explicit leakage threshold. The unprotected map O·xi over GF(16) is evaluated against a masked and row-shuffled variant under an identical acquisition procedure. Test Vector Leakage Assessment (TVLA) of the unprotected map peaks at |t|=52.88 fixed-versus-random and at |t|=195.7 under a secret-dependent fixed-versus-fixed test, while a non-profiled Correlation Power Analysis (CPA) resolving the multiplicative-identity alias and temporal row-mixing collapses the first key row from 168 to 24 candidates, with a median of 287 measured across 20 independent random keys. The proposed countermeasure pairs masking with per-pass row shuffling, in order to suppress the micro-architectural residue masking alone leaves; it realizes a leakage reduction approaching 54×, to |t|=3.62 with no failing point out of 24,000, at roughly 2.22× cycles. The evaluation is a laboratory assessment of the isolated map on an STM32F303 (ARM Cortex-M4) measured with a ChipWhisperer-Lite, and does not exercise complete MAYO signing.