Design of high-precision, low-power energy metering integrated circuits based on TDM architecture

Purpose With the rapid development of smart grids and renewable energy, higher requirements are placed on the accuracy and efficiency of power metering. To address the limited accuracy of traditional analog-to-digital converter sampling schemes and the large size and high cost of discrete-component time-division multipliers (TDM), this study aims to design a high-precision, low-power power metering integrated circuit based on a TDM architecture, which achieves monolithic integration while maintaining superior metering performance. Design/methodology/approach Using frequency domain modeling, the core modules of the system are abstracted into an oversampling modulator and a multiplier. The sources of error, such as phase shift, nonlinearity and quantization noise, are accurately analyzed. A phase-shift-free pulse width modulator structure and a notch filter optimized using the root locus method are proposed to compensate for phase errors and suppress harmonic interference. Findings Simulation results show that under typical process angles and room temperature conditions, the chip metering error is 21.25 ppm and the error does not exceed 33.07 ppm across all process angles and within a temperature range of −40°C to 85°C. Under 10% total harmonic distortion conditions, the suppression errors for the third and fifth harmonics are better than 45 and 52 ppm, respectively. The total system power consumption is 11.8 mW, with the analog core power consumption being less than 9.8 mW. This integrated circuit outperforms traditional digital solutions in terms of accuracy, integration and power consumption, providing an effective monolithic integrated solution for high-precision power metering in smart grids. Originality/value This study presents an original monolithic integrated solution for high-precision power metering by combining a TDM architecture with advanced error compensation techniques. The proposed phase-shift-free pulse width modulation structure and root-locus-optimized notch filter effectively improve measurement accuracy and harmonic suppression while maintaining low power consumption. Compared with conventional digital-based metering solutions, the developed chip achieves superior integration, accuracy and energy efficiency, providing a practical and scalable approach for next-generation smart grid power measurement systems.