Thermal Bottleneck Identification and Parameter Impact Analysis of Internal Packaging Layers in Liquid-Cooled IGBT Modules

To address the challenge of quantitatively identifying thermal-resistance contributions from multi-layer packaging structures within liquid-cooled insulated-gate bipolar transistor (IGBT) modules, this study establishes a three-dimensional conjugate heat-transfer model incorporating the chip, solder layer, direct-bonded copper (DBC) ceramic layer, substrate, elliptical pin-fin heat sink, and fluid domain. The IGBT and fast-recovery diode (FRD) power losses under typical motor controller operating conditions are modeled as volumetric heat sources applied to the chip region. Based on model validation, an internal thermal bottleneck evaluation method is proposed using inter-layer temperature-drop decomposition, introducing the thermal bottleneck number (BN) to quantify the temperature-drop contribution of each packaging layer along the target chip’s heat-dissipation path. Results show that in the baseline structure, the DBC ceramic layer is the critical internal thermal bottleneck, with a BN value of 11.05%. When the DBC thermal conductivity increases from 20 W/(m·K) to 80 W/(m·K), the maximum junction temperature of the IGBT decreases from 413.32 K to 396.79 K, and the BN drops from 11.05% to 3.69%. Conversely, when the DBC thickness increases from 0.20 mm to 0.50 mm, the maximum junction temperature rises from 405.45 K to 424.42 K. Further analysis reveals that after weakening the DBC thermal bottleneck, the relative temperature-drop contribution of the solder interface becomes increasingly apparent; notably, a central 20% low-conductivity defect in the solder layer raises the maximum junction temperature to 517.16 K, 103.84 K higher than under normal solder conditions. These findings provide valuable insights for identifying internal thermal bottlenecks and optimizing packaging structures in liquid-cooled IGBT modules.