Lightweight Dickson Modular Multiplication Using Regular Systolic Arrays for Resource-Restricted IoT Infrastructure

As the deployment of Internet of Things (IoT) ecosystems accelerates, safeguarding distributed networks against pervasive security and privacy threats has become a paramount concern. Integrating robust cryptographic protocols directly onto resource-limited edge devices offers a promising line of defense. However, severe hardware constraints historically complicate practical implementation. Because finite-field arithmetic fundamentally dictates the speed and efficiency of these cryptographic primitives, optimizing underlying multiplication techniques remains critical. To address these challenges, this paper presents an innovative, highly regular bit-serial systolic architecture tailored specifically for Dickson modular multiplication in binary extension fields. This is achieved via a streamlined systolic mapping over GF(2l) using dependency graph extraction, scheduling vectors, and projection directions. With localized pathways, the structure is highly optimized for VLSI integration. The performance and effectiveness of the proposed system are thoroughly evaluated and validated through comprehensive simulation results. Based on analytical and gate-level modeling, the design significantly enhances efficiency, lowering area by at least 162.8%, power by at least 214.3%, Area–Time Product by at least 5%, and Time–Power Product by at least 25.6%. These findings confirm that the proposed architecture substantially outperforms state-of-the-art bit-serial multipliers across these key evaluation metrics. Consequently, this solution serves as an ideal cryptographic engine for tightly constrained IoT hardware and embedded nodes, reinforcing secure and energy-aware data processing. By fostering resilient infrastructure and green digital practices, the work directly supports sustainable digital transformation and robust edge computing security.