A VCO using a gain‑enhancement circuit

A 0.9-V low-power VCO using TSMC 0.18-μm CMOS process has been proposed. A gain‑enhancement circuit and an LC harmonic‑enhancement circuit are introduced to lower phase noise. The drain current of the tail transistors is shaped by the differential fundamental signals from the cross-coupled pair. The second‑order harmonic signal at the drains of the tail transistors can be enlarged with the LC harmonic‑enhancement circuit. The proposed gain‑enhancement circuit reuses the enlarged second‑order harmonic signal to increase the differential fundamental signal power without extra power consumption. The proposed gain‑enhancement circuit can provide higher output impedance and voltage gain than conventional common-source cross-coupled pair. The measured results show that the phase noise at 1 MHz offset frequency from the carrier signal is −119.2 dBc/Hz with 1/f3 corner frequency of 21 kHz, while the control voltage is 0.5 V. The frequency tuning range is from 2.29 to 2.37 GHz under power consumption of 1 mW. The figure of merit at 1 MHz offset frequency from the carrier signal is −187 dBc/Hz.