High‐Performance Top‐Gate SnO 2 Transistors Enabled by Defect Modulation and Interface Engineering Using Atomic Layer Deposition

ABSTRACT Achieving high‐performance SnO 2 field‐effect transistors remains challenging due to the difficulty in simultaneously achieving effective carrier control and efficient carrier transport. Here, we address this challenge by combining spatial defect modulation and dielectric interface engineering in top‐gate SnO 2 field‐effect transistors using atomic layer deposition (ALD). A super‐cycle ALD process enabled spatially controlled Al incorporation at the bottom, middle, or top of a SnO 2 channel, enabling precise modulation of oxygen vacancy‐related defects and carrier concentration. Structural and spectroscopic analyses confirm the vertical confinement of Al dopants and the reduction of oxygen vacancy states. Among the configurations, bottom‐positioned Al incorporation provides optimized channel characteristics, delivering an on/off current ratio of ∼10 5 and a threshold voltage of −0.8 V. To further enhance carrier transport, the influence of HfO 2 , ZrO 2 , and Al 2 O 3 gate dielectrics was investigated in a top‐gate architecture. While devices with HfO 2 and ZrO 2 exhibit comparable electrical characteristics, those employing Al 2 O 3 show a mobility enhancement up to ∼34 cm 2 /V·s. This improvement is attributed to interfacial charge modulation at the Al 2 O 3 /SnO 2 interface, where defect‐mediated carrier supply enhances channel accumulation while mitigating impurity scattering. These results demonstrate that synergistic control of bulk defects and dielectric interfaces provides an effective pathway toward high‐performance SnO 2 transistors.