Multicore Progressive Product Reduction Modular Multiplication to Secure Assistive Devices Sustaining Future Economies

The rapid expansion of the Internet of Medical Things (IoMT) and intelligent assistive technologies has intensified the need for resource-optimized cryptographic hardware to protect sensitive biometric data. Cryptographic hardware performance relies primarily on modular arithmetic operations, especially field multiplication. Although the binary extension field provides carry-less arithmetic ideal for battery-powered devices, standard general-purpose processors lack the dedicated hardware required to execute these operations efficiently. This paper proposes a novel multicore-based modular multiplication algorithm that bridges this gap by exploiting the parallel coordination fabric and high-bandwidth interconnects of modern embedded multicore systems. Central to this work is the Progressive Product Reduction (PPR) paradigm, which optimizes hardware efficiency by integrating the multiplication and field reduction phases into a unified process, thereby minimizing intermediate data storage and computational depth. We introduce and analyze two distinct architectural strategies—Progressive Product Reduction with Column Division (PPR-CD) and Progressive Product Reduction with Row Division (PPR-RD)—and establish rigorous mathematical models to estimate hardware area, critical path delay, and exact operational latency across various core configurations. Our performance evaluation demonstrates that the PPR-RD architecture achieves superior Area-Delay Product (ADP) and energy efficiency, providing a scalable framework for securing sensitive biometric data in next-generation assistive devices. This implementation ensures robust cryptographic protection for assistive devices while maintaining energy autonomy and computational resilience essential for sustaining consumer trust, advancing global health equity, and driving financial stability in future digital economies.