An On-Chip Continuous Entropy-Quality Monitoring Method for Random-Number Source Output Streams

The output quality of random-number sources directly affects the security of cryptographic systems. Physical-noise degradation, environmental disturbance, device aging, and fault injection may increase output bias, correlation, and predictability. This paper presents a resource-conscious on-chip entropy-quality supervisor for random-number source output streams. The design uses non-overlapping 1024-bit measurement windows and a shared feature engine for bit counts, directional transition counts, and run information. These features support repetition-count, adaptive-proportion, and low-toggle checks, together with two-bit pattern-concentration and first-order conditional-transition indicators, exponentially weighted moving-average trend monitoring, comprehensive scoring, and a seven-bit alarm bitmap. The RTL accepts a 32-bit valid-data interface, makes one decision every 32 valid words, and is integrated into an Artix-7 XC7A35T project configured with a 50 MHz system-clock constraint. The complete project includes a ring-oscillator TRNG, and controlled deterministic fault patterns are inserted into selected windows of the TRNG stream for fault-response verification. Deterministic RTL simulations show complete alarm mappings of 0111111 for fixed-value patterns, 0011000 for an isolated alternating window, and 1011000 for the fourth consecutive alternating window. A parameterized capture simulation also verifies pre-event, injection, and recovery sequencing. FPGA implementation results show that the entropy-supervisor core uses 1009 LUTs and 276 flip-flops without BRAM or DSP resources, while the complete project uses 1313 LUTs, 614 flip-flops, and one BRAM tile. The design meets the 50 MHz clock constraint with a WNS of 1.079 ns and no setup or hold violations. The total on-chip power reported by Vivado is 0.076 W; without simulation-derived switching activity, this value is approximate and is not a board measurement. The results establish the functional behavior of the monitoring and decision paths. The two-bit pattern-concentration and first-order conditional-transition indicators are empirical tools for online anomaly diagnosis; neither is a min-entropy estimator, and they do not replace source-specific entropy assessment under NIST SP 800-90B.

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Publication Details

Journal
Electronics
Published
2026-09-10
DOI
https://doi.org/10.3390/electronics15184101
Primary Topic
Chaos-based Image/Signal Encryption
Type
article
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article

An On-Chip Continuous Entropy-Quality Monitoring Method for Random-Number Source Output Streams

Penghui Guan, Xianli Xie, Xingbin Wang, Jiajun Zhou et al.
Electronics
Chaos-based Image/Signal Encryption
article

An On-Chip Continuous Entropy-Quality Monitoring Method for Random-Number Source Output Streams

Penghui Guan, Xianli Xie, Xingbin Wang, Jiajun Zhou, Haibo Wu, Tianhao Yan, Jiansheng Chen
article en

Abstract

The output quality of random-number sources directly affects the security of cryptographic systems. Physical-noise degradation, environmental disturbance, device aging, and fault injection may increase output bias, correlation, and predictability. This paper presents a resource-conscious on-chip entropy-quality supervisor for random-number source output streams. The design uses non-overlapping 1024-bit measurement windows and a shared feature engine for bit counts, directional transition counts, and run information. These features support repetition-count, adaptive-proportion, and low-toggle checks, together with two-bit pattern-concentration and first-order conditional-transition indicators, exponentially weighted moving-average trend monitoring, comprehensive scoring, and a seven-bit alarm bitmap. The RTL accepts a 32-bit valid-data interface, makes one decision every 32 valid words, and is integrated into an Artix-7 XC7A35T project configured with a 50 MHz system-clock constraint. The complete project includes a ring-oscillator TRNG, and controlled deterministic fault patterns are inserted into selected windows of the TRNG stream for fault-response verification. Deterministic RTL simulations show complete alarm mappings of 0111111 for fixed-value patterns, 0011000 for an isolated alternating window, and 1011000 for the fourth consecutive alternating window. A parameterized capture simulation also verifies pre-event, injection, and recovery sequencing. FPGA implementation results show that the entropy-supervisor core uses 1009 LUTs and 276 flip-flops without BRAM or DSP resources, while the complete project uses 1313 LUTs, 614 flip-flops, and one BRAM tile. The design meets the 50 MHz clock constraint with a WNS of 1.079 ns and no setup or hold violations. The total on-chip power reported by Vivado is 0.076 W; without simulation-derived switching activity, this value is approximate and is not a board measurement. The results establish the functional behavior of the monitoring and decision paths. The two-bit pattern-concentration and first-order conditional-transition indicators are empirical tools for online anomaly diagnosis; neither is a min-entropy estimator, and they do not replace source-specific entropy assessment under NIST SP 800-90B.

ElectronicsVol. 15(18)
Tianjin University (CN), State Key Laboratory of Vehicle NVH and Safety Technology (CN)
Life in Land
Openalex Percentile: Top 13%
Chaos-based Image/Signal Encryption
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