Uncertainty-Aware Machine Learning for Compact-Model-Based Design and Identifiability Analysis of WSe2 p-Channel Transistors

Machine-learning surrogates can accelerate transistor design, but optimized predictions require physical consistency and explicit treatment of surrogate uncertainty. Here, we develop an uncertainty-aware machine-learning framework for compact-model-based design of WSe2 p-channel field-effect transistors using an experimentally calibrated S2DS model. A 5000-device dataset spanning channel length, equivalent oxide thickness, hole mobility, contact resistance, impurity density, trap density, and gate-voltage offset was used to train a censor-aware neural-network surrogate for full p-branch transfer-curve prediction at two drain biases. On an independent 750-device test set, the surrogate achieved a mean pointwise R2 of 0.9891 and an exact-coordinate RMSE of 0.0799 decade. The framework further combined inverse-identifiability analysis, Sobol sensitivity analysis, and multiobjective optimization of saturation on-state current, saturation-bias maximum transconductance, normalized drain-bias threshold shift, and threshold-voltage placement. Screening of 262,144 candidate designs yielded 48 Pareto-optimal solutions, of which nine satisfied the uncertainty-screening criteria and six retained all four performance claims after direct S2DS reevaluation. These results demonstrate a physically grounded and uncertainty-aware approach for efficient WSe2 transistor design within an experimentally calibrated compact-model domain.