Emulation and Mitigation of Multiple bit errors in SRAM based Space FPGAs

Static random-access memory (SRAMs) systems are currently experiencing more failures as a result of the aggressive CMOS integration density. Burst faults in data are caused by different noises that affect data transmission in modern space communications. Therefore, the error correction codes (ECC) are essential for identifying and fixing faults. Nevertheless, the traditional error correction encoders and decoders only detected and fixed a single bit error with increasing latency. In this research, a novel triple modular redundancy based Multibit error correction code (TMR-MECC) has been proposed to protect SRAM memories against multiple upsets in space application. In the proposed method 2D ECC are used in the encoder-decoder stage to find the appropriate syndrome value to detect and correct the error. In addition to that 2-D ECC, TMR is incorporated to protect their codes. Hybrid ECC-TMR adds spare redundant codes to the conventional major ECC techniques. If any redundant codes which is faulty, the faulty codes are replaced by the spare codes that are already stored in the on-chip SRAM. Emulation can be done with the MBU injection and MBU mitigation techniques implemented on FPGA and the result analysis evaluated using MATLAB. The resources overhead analysis is conducted for kintex-7 and Spartan 3E FPGA due to its low power characteristics. The proposed method reduces LUT usage by 30.36%, 25.4%, 9.3% compared to IMC-ECC, SD-ECC, SEC-Hamming ECC for Spartan-3E FPGA respectively.