A Time-Decoupled PWM Implementation Architecture Based on Predictive Duty-Cycle Sequences for High-Switching-Frequency Three-Phase Buck Rectifiers

High-switching-frequency operation substantially reduces the available time for sampling, control computation, modulation mapping, PWM-register updating, and auxiliary interrupt operations in digitally controlled three-phase buck rectifiers. Given this, this paper presents a time-decoupled PWM implementation architecture (TD-PWM) based on predictive duty-cycle sequences that enables sufficient computational redundancy. In the proposed architecture, the sampled information is used to generate an N-element duty-cycle sequence for the following control period. The generated sequence is stored in a buffer and subsequently loaded into the PWM registers one element per switching period. Consequently, prediction, control calculation, and SVPWM mapping are performed at the control frequency, whereas the duty-cycle values are updated at the switching frequency. A two-timescale execution structure is implemented in which the control-period task performs sampling and sequence generation, while the high-priority switching-period task performs sequence indexing and PWM-register loading. Experimental validation is conducted on a 400 W three-phase buck-rectifier prototype with a switching frequency of 100 kHz, a control frequency of 20 kHz, and N = 5. Under the investigated operating conditions, the proposed architecture achieves an input-current THD of 2.06% and shorter measured settling times than the two reference implementations. The results demonstrate the feasibility of the proposed implementation architecture.