Automated Analog Layout Synthesis
Abstract In a world where analog design is becoming increasingly important, it is becoming increasingly important to provide solutions that can increase designer productivity by increasing the level of available automation. A particularly critical step is in generating the circuit layout, since circuit parasitics can greatly influence circuit performance. This paper presents an overview of recent progress in the area of automated analog layout synthesis, using the ALIGN layout synthesis to showcase a representative design methodology, and listing a set of open problems. An example of how ALIGN is used to synthesize an RF MIMO circuit with enhanced designer productivity is shown, and recent developments on expanding from layout synthesis to automated optimization, with layout in the loop, are overviewed.
Authors
- Jitesh Poojary (ORCID: https://orcid.org/0000-0001-7548-9064)
- Ramesh Harjani (ORCID: https://orcid.org/0000-0001-7691-566X)
- Sachin S. Sapatnekar (ORCID: https://orcid.org/0000-0002-5353-2364)
- S. Ramprasath
- Surya Srikar Peri
- Subhadip Ghosh
- Jiang Hu
- Sosina Abiyot Berhan
- Endalk Gebru
Institutions
- University of Minnesota (US)
- Indian Institute of Technology Madras (IN)
- Texas A&M University (US)
Publication Details
- Journal
- Journal of the Indian Institute of Science
- Published
- 2026-09-05
- DOI
- https://doi.org/10.1007/s41745-026-00514-x
- Primary Topic
- VLSI and FPGA Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Science Foundation