Role of Hole Dynamics in Polarization Reset and Switching-Assist Pulse-Based Erase Optimization of Floating Body Ferroelectric Field-Effect Transistors

Abstract HfO2-based floating body (FB) ferroelectric field-effect transistors (FeFETs) have attracted growing interest owing to their applicability across a broad range of applications, including embedded nonvolatile memory, advanced logic device, and high-density storage memory. However, efficient erase (ERS) operation in these devices is fundamentally hindered by the absence of a direct hole supply to the isolated FB, and the mechanisms governing alternative hole generation pathways and their role in polarization reset remain poorly understood. In particular, insufficient hole generation and supply to the floating string channel during block-level ERS operations of three-dimensional ferroelectric NAND (3D FeNAND) impose significant constraints on both ERS voltage and ERS speed, underscoring the need for a deeper understanding of hole dynamics.In this work, the key enabler for ERS operation in FB FeFETs is systematically identified by clarifying the correlation between hole dynamics and polarization reset. In-depth electrical characterization of silicon-on-insulator FeFETs reveals that, in conventional ERS schemes employing a negative gate bias, polarization reset is driven by gate-to-source/drain band-to-band tunneling-induced hole generation, while subsequent hole accumulation in the FB leads to anomalous threshold voltage (Vth) transitions. To improve ERS efficiency, a switching-assist pulse scheme is proposed, which enhances both reset speed and reset degree at a reduced ERS voltage. These findings offer practical design guidelines for optimized ERS schemes in high-density 3D FeNAND.