On-Chip Measurement Circuit for Single-Event Transient Sensitivity and Propagation in 130 nm Flash-Based FPGAs

This paper proposes an on-chip time-to-digital converter (TDC) named pulse delay and capture circuit (PDCC), dedicated to single-event transient (SET) pulse measurement for radiation characterization of flash-based FPGAs. To address the inherent trade-offs of mainstream vernier delay line (VDL) and snapshot TDC schemes, the proposed PDCC employs a 16-stage single-chain self-triggering capture circuit with a SET indicator flip-flop, incorporates heterogeneous-cell ring-oscillator-based process-voltage-temperature (PVT) calibration, and avoids the need for resource-intensive first-in-first-out (FIFO) buffers. Implemented on a 130 nm A3PE600 flash-based FPGA, the PDCC achieves a nominal theoretical resolution of 640 ps and a nominal theoretical dynamic range of 0.64–10.24 ns, with 53.5% lower logic resource overhead than the VDL benchmark. Heavy-ion irradiation experiments validate the measurement capability and reveal asymmetric SET pulse propagation evolution characterized by positive-pulse broadening and negative-pulse attenuation, as well as sensitivity disparities among logic gates, which are attributed to the physical implementation of internal transistor networks within the VersaTile. A multi-criteria assessment based on the Simple Additive Weighting (SAW) method, evaluating resolution, dynamic range, logic resource overhead, and measured SET pulse width, yields an overall performance score (OPS) of 1.43, corresponding to a 43% higher score relative to the VDL baseline.