A low power dynamic latch comparator with grounded reset for gigahertz analog to digital conversion in 180 nm CMOS

Dynamic regenerative comparators are widely used in high-speed and low-power analog-to-digital converters (ADCs) due to their zero static power consumption, compact area, and fast decision capability. However, conventional dynamic comparator architectures often suffer from excessive power consumption, large delay, kickback noise, and complex clocking schemes, which limit their performance in GHz-range ADC applications. In this paper, a new low-power dynamic latch comparator is proposed, featuring a simplified current-mode regenerative structure combined with an efficient grounded reset technique. The proposed comparator is based on the StrongARM family and employs a minimal two-transistor cross-coupled latch along with a simple readout buffer, significantly reducing circuit complexity, parasitic capacitance, and power consumption. By resetting the output nodes directly to ground, the proposed architecture enables faster regeneration, lower offset, and improved robustness against process variations while eliminating the need for multiple clock phases. In addition, comprehensive analytical expressions for delay, power consumption, and kickback noise are derived to provide deeper insight into the circuit behavior. Post-layout simulations in a 0.18-µm CMOS technology demonstrate that the proposed comparator achieves reliable operation at a clock frequency of 1 GHz with a power consumption of 65.1 µW, a delay of 370.4 ps, a kickback noise of 17.9 mV, and an active core area of only 188.2 μm 2 at a 1.8 V supply voltage. Comparative results confirm that the proposed design offers a favorable trade-off between speed, power efficiency, and area when compared with conventional StrongARM, Lewis-Gray, and Elzakker dynamic comparators, making it a suitable candidate for high-speed and energy-efficient ADC applications.