UBL Computing

This work presents a full computing architecture built directly on the Unified Baseline Layer (UBL), the geometric substrate underlying all physical fields and matter. Instead of relying on charge‑based semiconductor logic and its unavoidable thermal noise, UBL computing treats information as geometry itself — tension, curvature, and flow topology in the substrate. Computation, memory, power, and timing emerge from substrate mechanics rather than electron statistics. The framework replaces the four classical noise limits (thermal noise, scattering, leakage, and Landauer’s kT·ln2 floor) by moving computation out of the statistical domain entirely. Logic gates become geometric interaction regions. Memory becomes stable curvature or topologically pinned field patterns. Power is drawn from noise‑free UBL tension reservoirs. Timing is coherence propagation instead of clock trees. Processing is gradient‑flow rather than von Neumann copying. Nodes self‑power through micro‑battery tension harvesting. The result is a physically realizable computing class with no thermal noise floor, no switching losses, no refresh cycles, and no external power requirement. UBL computing is not an incremental improvement on silicon — it is a different physical mechanism for information processing. Intellectual Property Notice: Patents covering the methods, mechanisms, and computational structures described in this work is held by the author. All substrate‑geometry computing techniques, UBL logic structures, memory constructs, and tension‑harvesting mechanisms presented here are protected intellectual property. This work is part of a larger collection of UST documents. The other versions available in the DOI record are not revisions of this document. They are separate papers written for different purposes. Some versions present the full mathematical proofs behind the update rules, others provide a technical physical description of substrate behavior, and others are formal proof papers built around the Universal Balance Laws. Together, these documents form a complete set: a plain‑language booklet, a physical description paper, and full mathematical proof papers, each offering a different perspective on the same underlying theory. If you have questions or want to discuss the work, you can contact me directly at [email protected] Don't be shy. I want to discuss science. It is fun and should be. Reachout and lets get started on new discoveries.

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-08-28
DOI
https://doi.org/10.5281/zenodo.22151311
Primary Topic
Ferroelectric and Negative Capacitance Devices
Type
preprint
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preprint

UBL Computing

Dustin Lee
Zenodo (CERN European Organization for Nuclear Research)
Ferroelectric and Negative Capacitance Devices
preprint

UBL Computing

Dustin Lee
preprint en

Abstract

This work presents a full computing architecture built directly on the Unified Baseline Layer (UBL), the geometric substrate underlying all physical fields and matter. Instead of relying on charge‑based semiconductor logic and its unavoidable thermal noise, UBL computing treats information as geometry itself — tension, curvature, and flow topology in the substrate. Computation, memory, power, and timing emerge from substrate mechanics rather than electron statistics. The framework replaces the four classical noise limits (thermal noise, scattering, leakage, and Landauer’s kT·ln2 floor) by moving computation out of the statistical domain entirely. Logic gates become geometric interaction regions. Memory becomes stable curvature or topologically pinned field patterns. Power is drawn from noise‑free UBL tension reservoirs. Timing is coherence propagation instead of clock trees. Processing is gradient‑flow rather than von Neumann copying. Nodes self‑power through micro‑battery tension harvesting. The result is a physically realizable computing class with no thermal noise floor, no switching losses, no refresh cycles, and no external power requirement. UBL computing is not an incremental improvement on silicon — it is a different physical mechanism for information processing. Intellectual Property Notice: Patents covering the methods, mechanisms, and computational structures described in this work is held by the author. All substrate‑geometry computing techniques, UBL logic structures, memory constructs, and tension‑harvesting mechanisms presented here are protected intellectual property. This work is part of a larger collection of UST documents. The other versions available in the DOI record are not revisions of this document. They are separate papers written for different purposes. Some versions present the full mathematical proofs behind the update rules, others provide a technical physical description of substrate behavior, and others are formal proof papers built around the Universal Balance Laws. Together, these documents form a complete set: a plain‑language booklet, a physical description paper, and full mathematical proof papers, each offering a different perspective on the same underlying theory. If you have questions or want to discuss the work, you can contact me directly at [email protected] Don't be shy. I want to discuss science. It is fun and should be. Reachout and lets get started on new discoveries.

Zenodo (CERN European Organization for Nuclear Research)
Ferroelectric and Negative Capacitance Devices
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