A 1.3‐μW/MHz, 3.76‐ppm/°C Decoupled FLL‐Based Oscillator in 180‐nm CMOS

ABSTRACT This paper presents a fully integrated, high‐precision frequency‐locked loop (FLL)–based oscillator. To resolve the fundamental trade‐off between high‐frequency clock generation and dynamic power overhead, a decoupled architecture is proposed: A 67.64‐MHz master clock is generated, while a divide‐by‐16 mechanism seamlessly drives a switched‐capacitor frequency‐to‐voltage converter (FVC). Within the loop, a double chopper stabilization technique is employed to eliminate temperature‐sensitive offsets and 1/ f noise. Furthermore, a process‐compatible composite resistor network combining positive and negative temperature coefficients is employed to cancel residual passive thermal drifts. Verified through post‐layout simulations in a 180‐nm standard CMOS process, the proposed design exhibits an outstanding temperature stability of 3.76 ppm/°C (−40°C to 125°C) and a 0.90%/V line sensitivity. Dissipating 87.7 μW with an active core area of 0.119 mm 2 , the design yields a highly competitive FoM of 173.1 dB.