Design and Implementation of a Low-Cost, Low-Power FPGA and RFID-Based Remote Vehicle Speed Detection System

This paper contributes a novel RFID-FPGA architecture for vehicle detection and speed measurement systems providing a theoretical framework and experimental evidence of the optimization of read zones of RFID antennas employed in traffic control. Contrary to other methodologies in which the positioning of the RFID antenna is taken empirically, the novelty of this study consists in determining the optimal read zone of the antenna by mathematical modeling employing the Friis transmission equation. This model will then be implemented in FPGA technology employing HDL programming language, thus allowing deterministic and reprogrammable estimation of the velocity of the vehicle. Experimental data obtained for motorbikes provide measurement accuracy of ±1 km/h with time resolution of 10 ms. Some of the novelties introduced in this work include the fact that the distance between the RFID antenna and the vehicle determines the maximum speed of the latter that can be detected. Moreover, the proposed FPGA-based architecture allows dynamic reconfiguration according to changing traffic conditions.