C-PathGen: An Efficient CPU-Parallel Critical Path Generation Algorithm

Critical Path Generation (CPG) is fundamental for many static timing analysis (STA) applications. As the circuit complexity continues to increase, CPG runtime has quickly become the bottleneck due to its time-consuming and iterative nature. Despite many CPG algorithms introduced by existing timers, nearly all of them are limited to a single CPU thread , leading to long runtime for large CPG queries. To mitigate this runtime challenge, we need a parallel CPG algorithm. However, designing a parallel CPG algorithm is very challenging because we need to strategically partition the path search space into multiple groups that can run in parallel while accommodating different slack priorities. To overcome this challenge, we propose C-PathGen , an exact and efficient CPU-parallel CPG algorithm. Building on our prior CPU-parallel CPG algorithm, PathGen, C-PathGen overcomes its inaccuracy by filtering out non-critical paths. Additionally, to eliminate contention caused by atomic operations on generated paths, we introduce a new exploration strategy that processes the paths directly in place. Compared to PathGen, C-PathGen is 6.8 × –10.3 × faster while producing exact results when dealing with large path queries on industrial circuit graphs.

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Publication Details

Journal
ACM Transactions on Design Automation of Electronic Systems
Published
2026-08-27
DOI
https://doi.org/10.1145/3844513
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
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article

C-PathGen: An Efficient CPU-Parallel Critical Path Generation Algorithm

Yibo Lin, Cheng-Hsiang Chiu, Wan Luan Lee, Boyang Zhang et al.
ACM Transactions on Design Automation of Electronic Systems
VLSI and FPGA Design Techniques
article

C-PathGen: An Efficient CPU-Parallel Critical Path Generation Algorithm

Yibo Lin, Cheng-Hsiang Chiu, Wan Luan Lee, Boyang Zhang, Zizheng Guo, Dian-Lun Lin, Tsung‐Wei Huang, Che Chang, Yi-Hua Chung
article en

Abstract

Critical Path Generation (CPG) is fundamental for many static timing analysis (STA) applications. As the circuit complexity continues to increase, CPG runtime has quickly become the bottleneck due to its time-consuming and iterative nature. Despite many CPG algorithms introduced by existing timers, nearly all of them are limited to a single CPU thread , leading to long runtime for large CPG queries. To mitigate this runtime challenge, we need a parallel CPG algorithm. However, designing a parallel CPG algorithm is very challenging because we need to strategically partition the path search space into multiple groups that can run in parallel while accommodating different slack priorities. To overcome this challenge, we propose C-PathGen , an exact and efficient CPU-parallel CPG algorithm. Building on our prior CPU-parallel CPG algorithm, PathGen, C-PathGen overcomes its inaccuracy by filtering out non-critical paths. Additionally, to eliminate contention caused by atomic operations on generated paths, we introduce a new exploration strategy that processes the paths directly in place. Compared to PathGen, C-PathGen is 6.8 × –10.3 × faster while producing exact results when dealing with large path queries on industrial circuit graphs.

ACM Transactions on Design Automation of Electronic Systems
University of Wisconsin–Madison (US), Peking University (CN), Cadence Design Systems (United States) (US)
Industry, innovation and infrastructure
Openalex Percentile: Top 19%
VLSI and FPGA Design Techniques
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C-PathGen: An Efficient CPU-Parallel Critical Path Generation Algorithm — Yibo Lin, Cheng-Hsiang Chiu, et al. · ACM Transactions on Design Automation of Electronic Systems (2026) | TGRS Research Map | TGRS