Dual modulation strategy for capacitor size reduction and voltage balancing in five-level inverter

Switched-capacitor-based level-doubling networks are widely employed in cascaded multilevel inverters to increase the number of output voltage levels using only two additional switches. However, the switched capacitors undergo charging and discharging during every half cycle of the fundamental output voltage, resulting in large capacitance requirements and increased capacitor voltage ripple. This work aims to reduce the capacitance requirement while preserving the level-doubling capability and output voltage quality. To achieve this, a full-bridge-based level-doubling network is employed instead of the conventional half-bridge configuration, enabling additional switching states for flexible capacitor control. A dual modulation strategy is further proposed to regulate the capacitor charging and discharging actions within every carrier cycle, thereby reducing the charge associated during the discharge interval. The proposed approach is validated through detailed simulation and experimental studies under varying modulation indices and load conditions. The results demonstrate that the proposed technique achieves a capacitance reduction by a factor of fcarrierfoutput, while maintaining capacitor voltage ripple and output voltage THD comparable to the conventional level-doubling network.

Authors

Publication Details

Journal
International Journal of Electronics Letters
Published
2026-08-27
DOI
https://doi.org/10.1080/21681724.2026.2724256
Primary Topic
Multilevel Inverters and Converters
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Dual modulation strategy for capacitor size reduction and voltage balancing in five-level inverter

Sakthisudhursun Balakrishnan, Swathi Subraja R, Harini V, Swathika Dinakaran
International Journal of Electronics Letters
Multilevel Inverters and Converters
article

Dual modulation strategy for capacitor size reduction and voltage balancing in five-level inverter

Sakthisudhursun Balakrishnan, Swathi Subraja R, Harini V, Swathika Dinakaran
article en

Abstract

Switched-capacitor-based level-doubling networks are widely employed in cascaded multilevel inverters to increase the number of output voltage levels using only two additional switches. However, the switched capacitors undergo charging and discharging during every half cycle of the fundamental output voltage, resulting in large capacitance requirements and increased capacitor voltage ripple. This work aims to reduce the capacitance requirement while preserving the level-doubling capability and output voltage quality. To achieve this, a full-bridge-based level-doubling network is employed instead of the conventional half-bridge configuration, enabling additional switching states for flexible capacitor control. A dual modulation strategy is further proposed to regulate the capacitor charging and discharging actions within every carrier cycle, thereby reducing the charge associated during the discharge interval. The proposed approach is validated through detailed simulation and experimental studies under varying modulation indices and load conditions. The results demonstrate that the proposed technique achieves a capacitance reduction by a factor of fcarrierfoutput, while maintaining capacitor voltage ripple and output voltage THD comparable to the conventional level-doubling network.

International Journal of Electronics Letters
Affordable and clean energy
Openalex Percentile: Top 19%
Multilevel Inverters and Converters
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.