An Implantable Charge Balanced Neurostimulator IC Using Standard CMOS Process

This paper presents the design of a bipolar current-mode stimulator integrated circuit (IC) for implantable prosthetic devices using 0.18-μm standard CMOS process. The proposed stimulator IC is capable of delivering up to 1-mA current through 10-kΩ load using 12.8 V supply voltage. The output impedance of the stimulator is enhanced by utilizing a regulated cascode output current driver stage, which achieves a voltage compliance of 12.4 V. In order to allow low-voltage standard transistors to operate reliably at high voltage, transistor stacking and dynamic gate biasing techniques are used. In addition, a simple active charge balancing circuit is included to achieve minimal net charge after stimulation cycle is complete. The overall layout area is 0.12 mm².

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Publication Details

Journal
IEIE Transactions on Smart Processing and Computing
Published
2026-08-27
DOI
https://doi.org/10.5573/ieiespc.2026.15.4.591
Primary Topic
Neuroscience and Neural Engineering
Type
article
Field-Weighted Citation Impact
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article

An Implantable Charge Balanced Neurostimulator IC Using Standard CMOS Process

Tuan Vo, Hyouk‐Kyu Cha
IEIE Transactions on Smart Processing and Computing
Neuroscience and Neural Engineering
article

An Implantable Charge Balanced Neurostimulator IC Using Standard CMOS Process

Tuan Vo, Hyouk‐Kyu Cha
article en

Abstract

This paper presents the design of a bipolar current-mode stimulator integrated circuit (IC) for implantable prosthetic devices using 0.18-μm standard CMOS process. The proposed stimulator IC is capable of delivering up to 1-mA current through 10-kΩ load using 12.8 V supply voltage. The output impedance of the stimulator is enhanced by utilizing a regulated cascode output current driver stage, which achieves a voltage compliance of 12.4 V. In order to allow low-voltage standard transistors to operate reliably at high voltage, transistor stacking and dynamic gate biasing techniques are used. In addition, a simple active charge balancing circuit is included to achieve minimal net charge after stimulation cycle is complete. The overall layout area is 0.12 mm².

IEIE Transactions on Smart Processing and ComputingVol. 15(4)
Affordable and clean energy
Openalex Percentile: Top 15%
Neuroscience and Neural Engineering
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