Binary‐to‐Ternary Reconfigurable Transistors Using Plasma‐Assisted MoS 2

ABSTRACT As the continued scaling of binary CMOS technology approaches fundamental physical limits, alternative computing frameworks are being explored to enhance information density and reduce circuit complexity. In particular, ternary logic, which can encode more information per device than binary systems, is an attractive candidate for energy‐efficient and highly integrated information processing systems. Herein, we present a binary‐to‐ternary reconfigurable transistor designed using a dual‐gated molybdenum disulfide (MoS 2 ) homojunction. By employing localized O 2 plasma treatment to the source and drain regions, a well‐defined intermediate state with weak gate dependence is created, achieving on/intermediate and intermediate/off current ratios of 10 2 and 10 4 , respectively. The ternary transistor, which can serve as a fundamental building block for diverse ternary logic gates, enables the implementation of a ternary inverter with an intermediate state tunable via a control gate. This tunability enables fine calibration for error correction and improves noise immunity. The ternary transistor can also be electrically reconfigured into a binary transistor, supporting binary‐to‐ternary interconnection in a highly simplified form. Utilizing the reconfigurable transistors, a new binary‐to‐ternary converter is introduced, which exhibits exceptional efficiencies in circuit complexity and energy consumption. Notably, the reconfigurable transistor is realized via scalable, CMOS‐compatible fabrication based on a simple MoS 2 homojunction.