Voltage Control Scheme to Mitigate Thermal Effects in Hybrid Bonding 3D NAND

Hybrid bonding-based 3D NAND Flash memory architectures suffer from severe threshold voltage (Vth) distribution broadening. This issue arises from vertical thermal gradients induced by the underlying peripheral circuits, which can compromise the read margin and endurance. In this work, we propose a voltage control scheme to overcome these challenges by incorporating a position-dependent gradient bias according to the temperature during the erase operation. Additionally, it employs a temperature-dependent adaptive pass voltage (Vpass) adjustment during the read operation. This approach mitigates temperature-dependent channel potential variations, thereby widening the narrowed read margin and improving cycling endurance. Through TCAD simulations, we analyzed the electrical characteristics of both body contact spacer (BCS) and channel-hole sidewall ONO butting (CSOB) structures. The Vth shift following the erase operation was suppressed from 200 mV to 10 mV for the BCS structure and from 850 mV to 10 mV for the CSOB structure. Verification under both matched and mismatched thermal scenarios demonstrated significant improvements. Consequently, we effectively narrowed the distribution width and enhanced the long-term cycling endurance of high-bit-density 3D NAND Flash memories.