Silicon Photonics for Co‐Packaged Optics: A Review of Core PIC Components and Industry Strategies

ABSTRACT Co‐packaged optics (CPO) has emerged as a pivotal technology for overcoming the bandwidth, power, and scalability bottlenecks of next‐generation AI and data center interconnects by closely integrating the optical engine (OE) with electronic chips (e.g., ASICs and XPUs). As a key component of the OE, photonic integrated circuits (PIC) are predominantly realized on the silicon photonics (SiPh) platform, which provides CMOS‐compatible fabrication, scalable heterogeneous integration, and the capability to implement full photonic functionalities on chip. Thus, this review presents a comprehensive overview of recent advances in core device‐level components of SiPh‐based PIC, including laser sources, Si‐based modulators, passive optical couplers, Ge‐on‐Si photodetectors, and multiplexers/demultiplexers, which significantly impact the performance of CPO systems. Industry strategies and representative system‐level demonstrations are also summarized to depict the current technological landscape. Furthermore, critical challenges and potential solutions for CPO system development are discussed, such as laser integration, thermal management, device reliability, bandwidth density, and energy efficiency. Together, these insights offer a device‐level roadmap for advancing CPO toward scalable, high‐performance, and economically viable deployment.