Robust Hybrid Four-to-Two CNFET Compressor Cells with Adaptive Threshold Control and Multiplier-Level Integration

This paper presents two novel robust hybrid energy-efficient hybrid 4-to-2 compressor cells, implemented in Carbon Nanotube Field-Effect Transistor (CNFET) technology. The proposed designs synergistically integrate transmissiongate multiplexers (TG-MUX), standard CMOS gates, and a new pass-transistor logic (PTL) XNOR/XOR module to achieve optimal performance and robustness. Extensive simulations using the Stanford CNFET model demonstrate significant improvements over the best existing designs. The second proposed compressor achieves 28.17% lower delay and 32.81% lower power-delay product (PDP) at 0.65 V. Furthermore, the cells exhibit superior resilience to process, voltage, and temperature (PVT) variations compared to all counterparts. When integrated into an 8×8 Dadda multiplier, the proposed compressors enable the multiplier to outperform the best prior design by 10.3% in delay and 13.8% in PDP. These results confirm the proposed compressors as robust, high-speed, and energy-efficient building blocks for next-generation CNFET-based arithmetic circuits.

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Publication Details

Journal
Journal of Circuits Systems and Computers
Published
2026-08-20
DOI
https://doi.org/10.1142/s0218126626502592
Primary Topic
Low-power high-performance VLSI design
Type
article
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article

Robust Hybrid Four-to-Two CNFET Compressor Cells with Adaptive Threshold Control and Multiplier-Level Integration

Mojtaba Maleknejad, Mehdi Bagherizadeh, Somayyeh Mohammadi
Journal of Circuits Systems and Computers
Low-power high-performance VLSI design
article

Robust Hybrid Four-to-Two CNFET Compressor Cells with Adaptive Threshold Control and Multiplier-Level Integration

Mojtaba Maleknejad, Mehdi Bagherizadeh, Somayyeh Mohammadi
article en

Abstract

This paper presents two novel robust hybrid energy-efficient hybrid 4-to-2 compressor cells, implemented in Carbon Nanotube Field-Effect Transistor (CNFET) technology. The proposed designs synergistically integrate transmissiongate multiplexers (TG-MUX), standard CMOS gates, and a new pass-transistor logic (PTL) XNOR/XOR module to achieve optimal performance and robustness. Extensive simulations using the Stanford CNFET model demonstrate significant improvements over the best existing designs. The second proposed compressor achieves 28.17% lower delay and 32.81% lower power-delay product (PDP) at 0.65 V. Furthermore, the cells exhibit superior resilience to process, voltage, and temperature (PVT) variations compared to all counterparts. When integrated into an 8×8 Dadda multiplier, the proposed compressors enable the multiplier to outperform the best prior design by 10.3% in delay and 13.8% in PDP. These results confirm the proposed compressors as robust, high-speed, and energy-efficient building blocks for next-generation CNFET-based arithmetic circuits.

Journal of Circuits Systems and Computers
Twitter (United States) (US)
Affordable and clean energy
Openalex Percentile: Top 18%
Low-power high-performance VLSI design
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