Low-Complexity MSB-Index LUT Digital Calibration for High-Resolution SAR ADCs

A digital calibration method with reduced LUT complexity is presented to suppress code-domain nonlinear errors caused by CDAC mismatch in high-resolution SAR ADCs. The method exploits the MSB-dominant and locally correlated behavior of mismatchinduced errors, so that interval-wise error estimation and correction can be performed using the most significant bits of the output code for LUT addressing. Unlike conventional MSB capacitor-weight calibration, the proposed method does not directly estimate individual capacitor errors; instead, it statistically compensates the code-domain error over MSB-indexed intervals. A segment-wise statistical training scheme is introduced for stable coefficient updating. The proposed method is evaluated by pre-layout circuitlevel simulations of a 16-bit SAR ADC designed in a 180 nm CMOS process. Under mismatch-dominant conditions, the SNDR, ENOB, and SFDR are improved from 76.24 dB, 12.37 bit, and 84.52 dB to 95.71 dB, 15.61 bit, and 107.41 dB, respectively. In addition, the required LUT size is reduced from 65536 entries to 4096 entries, corresponding to a storage reduction of approximately 93.75%. These results indicate that the proposed method can reduce LUT storage overhead while maintaining effective calibration accuracy under mismatch-dominant pre-layout simulation conditions.