Enhancement in Charge-Trapping Efficiency for InGaZnO Vertical-Channel Memory Transistors via Gate-Stack Engineering: Validation in the 40 nm Scaling Regime

The continuous demand for higher bit density in 3D NAND flash memory has accelerated the pursuit of Z-scaling as a means of managing total chip profiles. Amorphous In-Ga-Zn-O (a-IGZO) with a 0.49:1:1.73 atomic ratio, deposited at 200 °C, has been identified as a promising channel material for scaled devices; however, the efficient electrical erase operation remains a significant bottleneck. In this work, we demonstrate an ultra-scaled vertical charge-trap memory thin-film transistor (V-CTM TFT) integrating this a-IGZO channel and a nanocrystalline ZnO charge-trap layer. The introduction of an H2O-based Al2O3 tunneling layer (TL) resulted in the activation of interfacial trap-assisted tunneling, while simultaneously tailoring the bulk properties of the ZnO layer. This oxidant-driven TL engineering has been demonstrated to enhance charge injection via interfacial oxygen vacancies, as well as to tailor the trap states within the ZnO layer, facilitating an expanded memory window without complex hole injection. Optimized for devices with a channel length of 60 nm and validated in an ultra-scaled 40 nm regime, the V-CTM TFT achieved a substantial memory window (∼10 V) and stable triple-level cell operation despite aggressive scaling. Furthermore, excellent high-temperature operational reliability at 80 °C and high cell-to-cell reproducibility (both within-wafer and run-to-run) were confirmed, providing a highly reliable and reproducible design strategy for future high-density 3D memory architectures.