M^2 -DFU: Multi-Mode Dataflow Architecture for Adaptive and High-Efficiency Data Processing

The impending end of Moore’s Law and Dennard Scaling has prompted a shift in both industry and academia from general-purpose processors (e.g., CPUs and GPGPUs) toward specialized solutions. However, the diverse hardware requirements of edge computing make it challenging for existing specialized architectures to adapt to rapidly evolving algorithms, often prioritizing efficiency at the expense of generality. Our approach leverages the inherent advantages of software-defined dataflow mechanisms and integrates reconfigurable SIMD into the architecture to achieve high efficiency and flexibility in hardware for edge computing, surpassing ASIC architectures. In this work, we propose M ^2 -DFU (Multi-Mode Dataflow Unit), a flexible, highly efficient architecture with configurable multiple execution modes. First, we identify general and specific requirements for various edge applications, including convolutional neural networks (CNNs), digital signal processing (DSP), and typical scientific computing. Next, we design a flexible architecture with high configurability across multiple modes. Efficient and reconfigurable microarchitectural optimizations are implemented to achieve multilevel parallelism and ensure high hardware utilization. Compared to NVIDIA GPUs, M ^2 -DFU achieves an average improvement of up to 6.8 \times in energy efficiency for typical edge computing applications.