A Multi‐Kernel Polar Decoder Based on Semi‐Parallel Architecture and 2‐Bit Decoding Approach for 5G and Beyond Wireless Communication

ABSTRACT Polar codes are the error‐correcting codes adopted as the channel code for the control channel in fifth‐generation new radio (5G NR) standards. The polar code constructed using binary kernels is familiar in 5G and restricts the code length to powers of two. As 5G and beyond (B5G) applications demand higher flexibility, the multi‐kernel polar codes are chosen as a viable candidate. This work proposes a multi‐kernel (MK) polar decoder and analyzes the latency, utilization rate, and hardware utilization efficiency. The last stage of the architecture is replaced by a hard decision (HD) node that decodes two bits simultaneously. The proposed method uses a semi‐parallel architecture with fewer processing units to minimize the hardware resources. The processing unit (PU) consists of a binary processing element (PE) and a mixed PE to adapt to the different binary or ternary kernel stages during decoding. The PEs and the HD logic in the last stage are optimized with MUX‐based logic to reduce the critical path delay. The latency and utilization rate improved by 15%–26% compared to conventional architecture as code length varies from to 3888 and achieved a lower bit‐error rate (BER) of at 3.5 dB for . The decoder is synthesized and implemented on a Virtex‐6 FPGA board for a code length of and compared with other decoders. It is observed that the decoder has the advantage of lower look‐up tables (LUTs) and flip‐flops (FFs) with additional random‐access memory (RAM) usage and higher hardware utilization efficiency (HUE) compared to other existing decoders.