Over 600 °C operation of ion-implantation-based SiC bottom-gate JFETs

Silicon carbide (SiC) junction field-effect transistors (JFETs) are promising for high-temperature integrated circuits. However, conventional top-gate structures fabricated in semi-insulating SiC substrates suffer from low threshold voltage (Vth) controllability due to ion-channeling effects and leakage current at high temperature through semi-insulating substrates. In this study, the authors demonstrate an ion-implantation-based SiC JFET architecture that addresses both challenges. By adopting a bottom-gate structure, the deviation between the designed and actual Vth was significantly suppressed to less than 0.1 V at 673 K, owing to the effective compensation of the channeling tail. Furthermore, by integrating the bottom-gate design into a double-well structure on an n-type epitaxial layer, the off-state leakage current at high temperature was thoroughly suppressed by the p-n junction isolation. The leakage current density at 873 K (600 °C) of the double-well p-JFET (∼3×10−5 mA/mm) was much lower than that at 673 K (400 °C) of the p-JFET on the semi-insulating substrate (∼1×10−3 mA/mm).