A hybrid random forest–ANFIS framework for accurate power estimation in CMOS VLSI circuits

Accurate estimation of power is a main requirement throughout the use of Complementary Metal–Oxide–Semiconductor Very Large-Scale Integration (CMOS VLSI) because it determines how efficiently energy is used; how hot a device will get from high temperatures; whether a device will work properly over long periods of time its reliability. Conventional methods for estimating power rely on simulating designs and provide very good accuracy; however, they can also have significant computational complexity and time requirements, especially in large-scaled circuits. To address these challenges, this research develops an new framework for estimating power intelligently within the CMOS VLSI design space using a Random Forest-Assisted Adaptive Neuro-Fuzzy Inference System (RF-ANFIS) approach. The RF-ANFIS combines the use of Random Forest to determine the best features to include for predicting power with the non-linear learning capabilities of ANFIS and the fuzzy reasoning ability of ANFIS to enhance prediction accuracy and lower the complexity of the models being developed. To derive the data required by the newly developed models, power-related features such as gate count, switching activity, fan-in, fan-out, frequency at which the device will operate, voltage level at which the device receives its power, and load capacitance have been derived from existing design simulation benchmarks from the ISCAS’85, ISCAS’89, and ITC’99 benchmark suites. The uniqueness of this work resides in the integration of Random Forest with ANFIS to create a hybrid estimating approach and then utilize multiple validation methods on different benchmark circuit categories. Through experimentation, the newly developed RF-ANFIS model provided a prediction accuracy of 98.9% and outperforming conventional RF, CNN, ANN, and standalone ANFIS models. The proposed framework provides a scalable and AI-driven solution for early-stage power estimation and low-power VLSI design automation.