Approximation Friendliness: A New Metric for Smarter Hardware Design Approximation for High-Level Synthesis

Approximate computing exploits the inherent error tolerance of many applications to achieve significant improvements in area, energy, and performance. This work proposes a novel method to determine the smallest possible hardware design that satisfies a given maximum error threshold ( E max ) using High-Level Synthesis (HLS). HLS tools rely heavily on synthesis directives (pragmas) to control how arrays (e.g., RAMs, ROMs, registers), functions (e.g., inline, goto), and loops (e.g., full unroll, partial unroll, pipeline) are implemented. In this work we leverage this and introduce an automated, approximation-aware HLS design space exploration framework guided by an Approximation Friendliness Index (AFI), a static metric that can be computed efficiently. This index enables the rapid identification of hardware implementations generated by setting unique HLS pragma combinations, with high potential for approximation, allowing the proposed framework to approximate only the most promising designs rather than every variant generated during the exploration process. Finally, recognizing that many hardware systems are organized as dataflow architectures, where multiple components are connected sequentially (e.g., JPEG), we extend our approach to optimize the entire dataflows given as separated individual behavioral descriptions for HLS. The proposed method identifies the best pragma combinations and set of approximations in each description to minimize the overall design size while maintaining accuracy at the primary outputs of the dataflow within E max . Experimental results show that this approach leads to basically the same results as exhaustively approximating every new design, while being substantially faster.