Gate Dielectric Engineering in p‐Type WSe ₂ Junctionless Gate‐All‐Around MOSFET

Gate dielectric engineering is investigated in a p‐type WSe 2 junctionless gate‐all‐around (JL‐GAA) MOSFET (3 nm diameter, 2 nm oxide) using the FETtoy 2.0 simulator. Three high‐ κ dielectrics—Al 2 O 3 ( κ = 9), HfO 2 ( κ = 22), and ZrO 2 ( κ = 25)—are compared at 300 K under identical geometry, with hole effective mass 0.45 m 0 and threshold voltage −0.18 V. All three dielectrics yield near‐ideal subthreshold swing (62.72 mV/dec) and ultralow DIBL (7.28 mV/V), showing that JL‐GAA electrostatic integrity is governed by nanowire geometry rather than dielectric permittivity. Saturation ON‐current rises 25.4% with dielectric constant, from 34.7 μ A (Al 2 O 3 ) to 43.5 μ A (ZrO 2 ), driven by increased gate capacitance. The I ON / I OFF ratio exceeds 10 10 for all dielectrics, reaching 1.95 × 10 10 for ZrO 2 , while peak transconductance rises from 51 to 63 μ S. Band diagram and capacitance analyses confirm the hole accumulation mechanism and origin of the drive current enhancement. Comparison with published n‐type WSe 2 JL‐GAA devices confirms comparable subthreshold performance, supporting a WSe 2 complementary MOS pair. ZrO 2 emerges as optimal, offering the best drive current, I ON / I OFF ratio, and transconductance without subthreshold penalty.